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ASML EUV lithography monopoly is the deepest chokepoint in semiconductor manufacturing because 30 years of co developed precision optics created an unreplicable ecosystem that gates all leading edge chip production
ASML holds 100% of the EUV lithography market and 83% of all lithography. No other company on Earth manufactures EUV machines. Canon and Nikon compete only in older DUV lithography. This is not a typical market concentration — it is an absolute monopoly on the technology required for every chip at 5
CoWoS advanced packaging is the binding bottleneck on AI compute scaling because TSMC near monopoly on interposer technology gates total accelerator output regardless of chip design capability
The AI compute supply chain's binding constraint is not chip design — it's packaging. TSMC's Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology is required to integrate AI accelerators with HBM memory into functional modules. TSMC holds near-monopoly on this capability, and capacity is
HBM memory supply concentration creates a three vendor chokepoint where all production is sold out through 2026 gating every AI training system regardless of processor architecture
High Bandwidth Memory (HBM) is required for every modern AI accelerator — NVIDIA H100/H200/B200, AMD MI300X, Google TPU v5. Three companies produce all of it globally: SK Hynix (~50% market share), Samsung (~40%), and Micron (~10%). All three have confirmed their HBM supply is sold out through 2026.
TSMC manufactures 92 percent of advanced logic chips making Taiwan the single largest physical vulnerability in global technology infrastructure
TSMC fabricates approximately 92% of the world's most advanced logic chips (7nm and below). This includes virtually all AI accelerators (NVIDIA, AMD, Google TPUs), all Apple processors, and most leading-edge smartphone chips. No other concentration of critical manufacturing capability exists in any
semiconductor fab cost escalation means each new process node is a nation state commitment because 20B plus capital costs and multi year construction create irreversible geographic path dependence
Leading-edge semiconductor fabs now cost $20B+ to build and take 3-5 years to construct. TSMC's Arizona complex is projected at $40B+ for two fabs. Samsung's Taylor, Texas fab costs $17B. Intel's Ohio fabs are projected at $20B. These are not business investments — they are nation-state-level commit